
This example shows three different match conditions scheduled to happen at successive instants in time, chosen at 100,200,300.
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The first two transitions (events) toggle a different SCT output pin.
The third event clears both outputs and also limits the timer, i.e. it sets its value back to zero.

The effect of limiting the timer is proven to happen since without it, the counter would have to reach its maximum value and 
then overflow/roll over to zero before the first event valued at timer tick 100 would happen again. Instead it happens again 
after 100 timer ticks as desired.

The SCT is configured in unified mode (one single 32-bit counter).

